A common characteristic of computers and other digital electronic systems is the use of synchronous logic driven by at least one digital clock signal. Generally, a clock signal alternates between a logic “high” level and a logic “low” level at a selected frequency compatible with the logic circuit being driven. Typically, the clock signal is generated by an oscillator circuit driven by a crystal excited into oscillation by a direct-current (DC) power supply voltage. The use of the crystal often results in a highly stable frequency source that is accurate within a few parts per million.
However, despite the accuracy and stability most clock signals exhibit, hardware problems periodically arise which cause the clock signal to temporarily or permanently fail. Such failures may include significant changes in the voltage levels of the clock signal, unacceptable variations in frequency or phase of the clock signal (often termed “jitter”), or even complete loss of the clock signal. Any of these faults are likely to result in improper operation of the associated digital circuitry. While most low-end computing systems and other electronic equipment, such as home computers, personal digital assistants (PDAs), and the like, are affected by clock problems, loss of data resulting from such failures is rarely catastrophic. However, with mid-range and high-end computing systems, such as commercial database and communication servers, any data integrity problems or downtime associated with clock signal faults may result in significant loss of revenue and decreased customer satisfaction.
To protect against clock signal errors, some computer systems employ two independent clock signal sources in conjunction with a switch circuit to forward one of the clock signals to drive the system logic. Thus, if problems are detected with one clock signal, the other may be selected quickly as the system clock signal by way of the switch.
However, two independent clock signal sources with ostensibly the same frequency are likely to be out of phase with each other, and may also exhibit slightly different frequencies. As a result, merely switching from one clock signal to another may introduce signal glitches, runt pulses, and the like into the clock signal being output from the switch, again causing problems to the system logic. Thus, the output of the switch is often configured to drive a phase-locked loop (PLL) circuit designed to ignore such temporary problems in the selected clock signal while generating an output clock signal with the same frequency as the clock signal leaving the switch. Also, the PLL circuit is capable of introducing a small phase error into the selected clock signal to address a phase difference between the input clock signals.
Unfortunately, use of the PLL circuit often introduces additional jitter into the output clock signal beyond that of the original input clock signal. The PLL circuit may also interact with one or more other PLL circuits coupled with the output clock signal, potentially introducing cascaded PLL stability problems into each of the other PLL circuits involved.